September 17th, 2012, Imperial College London, London, UK
9th International Conference on Quantitative Evaluation of SysTems (QEST) 2012
At the same time, the computer industry is undergoing a major paradigm shift. Processor manufacturers are introducing new generations of multicore processor with large numbers of cores and high performance GPUs, cloud based computing resources are easily accessible, and external memory devices, such as hard disks or solid state disks, are getting more powerful.
It is inevitable that verification techniques and tools need to undergo a similarly deep technological transition to catch up with the new hardware architectures. This has created an increasing interest in parallelizing and distributing verification techniques.
The aim of the PDMC workshop series is to cover all aspects related to the verification and analysis of very large and complex systems using, in particular, methods and techniques that exploit current parallel hardware architectures. The PDMC workshop aims to provide a working forum for presenting, sharing, and discussing recent achievements in the field of high-performance verification.
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PROCEEDINGS & SUBMISSION GUIDELINES:
Final version will be published in Electronic Notes in Theoretical Computer Science. Please, prepare your final version according to the instructions given on the ENTCS macro page.
Submission page at EasyChair conference system.